A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board
George Charitopoulos, Dionisios N. Pnevmatikatos, Marco Domenico Santambrogio, Kyprianos Papadimitriou, Danilo Pietro Pau · Advances in parallel computing · 2016
During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential.