Real-time implementation of DVFS enhanced LEON3 MPSoC on FPGA
Zohaib Najam, Muhammad Yasir Qadri, Shaheryar Najam, Umar Shahbaz Khan · 2016
In the field of embedded system there exists a trade off between power/performance optimization, hence many heuristics and techniques were presented at various development levels such as hardware software co-design, schedulers and optimal code compilation. This paper presents an enhanced version of LEON3 architecture which includes support for run-time management of supply voltage and processor operating frequency. This enhancement can be useful to implement various DVFS driving algorithms in LEON3 architecture aiming to leverage power consumption and throughput. Frequency scaling on the fly is based on dynamically reconfigurable clock synthesis feature available in Xilinx FPGA Virtex-4 or higher. The implementation of DVFS in LEON3 architecture is driven and controlled by general-purpose I/O port attached to advanced peripheral bus (APB) to change processor frequency on the fly during the execution of application programs. The work is implemented as a prototype on a Xilinx FPGA platform and incurs very small hardware overheads.