HW/SW co-design of face detection & recognition on virtual platform
Mi-Young Lee, Youngseok Baek, Seongmin Kim, Hyuk Kim, Bontae Koo, Joohyun Lee · 2016
In this paper, we present a FPGA implementation of face detection hardware (HW) and also address face recognition software (SW) on virtual platform. We apply very deeply-cascaded classifier which is composed of heterogeneous feature-classifiers to capture various characteristics of images. We use 2 step classifiers, the first searches for the coarse features and the second for the fine features. Both of the features are composed of HAAR like feature classifiers and Gabor classifiers while the 1stcoarse classifier uses 700 classifiers and the 2nduses 1350 classifiers. For the very-deeply cascaded face detector, we developed dedicated HW engine to process a feature per a cycle. The face detection is implemented in a Xilinx Virtex-7 device. For face recognition SW co-design, we also developed a virtual platform (VP). We co-verified face detection engine and face recognition SW running on a conventional operating system (OS) using the VP. Face detector operates over 30 frame/s at 50 MHz frequency for real-time applications up-to 640×480 size image.