A post-processing algorithm for reducing strong error effects in NAND flash memory
Sung-Rae Kim, Ki-Jun Lee, Gyuyeol Kong, Myung-Kyu Lee, Dongmin Shin, Geunyeong Yu, Beomkyu Shin, Pilsang Yoon, Hongrak Son, Jun-Jin Kong · 2016
This paper introduces a novel post-processing algorithm for low-density parity-check (LDPC) codes adequate for NAND flash memory, to improve error correction capability of a soft decision decoding by reducing strong error effects in an efficient way. In this algorithm, it can detect variable nodes of strong errors using incoming check-to-variable (c2v) messages and reduce magnitude of channel reliability of the nodes to avoid supplying large erroneous variable-to-check (v2c) messages for the check nodes. The proposed post processing algorithm with a finite precision LDPC decoding scheme is named edge-based post processing and effectively reflects time varying characteristic of NAND flash channel.