Development of the Parallel BCH and LDPC Encoders Architecture for the Second Generation Digital Video Broadcasting Standards with Adjustable Encoding Parameters on FPGA
Tran Van Nghia · 2016
In the second generation digital video broadcast standards, such as DVB-T2, DVB-S2, DVB-C2, etc., is applied a powerful channel coding scheme to transmit data on the non-ideal communication channels with limited bandwidth due to the serial concatenation of BCH (Bose-Chaudhuri-Hocquenghen) and Low-Density-Parity-Check (LDPC) codes. The high-speed requirements, long data block lengths and multi-parametric encoding present complex challenges in the efficient implementation of a hardware architecture. This paper proposes a new approach to parallel implementation of BCH and LDPC encoders with adjustable encoding parameters, supporting all the different BCH + LDPC code configurations. The proposed solution is fully backward compatible to legacy decoder on the receiving side.