BluSTL: Controller Synthesis from Signal Temporal Logic Specifications
Alexandre Donzé, Vasumathi Raman · EPiC series in computing · 2018
We present BluSTL, a MATLAB toolbox for generating controllers from specifications written in Signal Temporal Logic (STL). The toolbox takes as input a system and a set of constraints expressed in STL and constructs an open-loop or a closed-loop (in a receding horizon or Model Predictive fashion) controller that enforces these constraints on the system while minimizing some cost function. The controller can also be made reactive or robust to some external input or disturbances.