Design & verification of ONFI complient high performance NAND flash controller
Akash Kumar, Jitendrabhai Ardeshana, Santosh Jagtap · 2016
We are living in the world where we are surrounded by electronic gadgets with the expectation for more compact size and performance. The NAND flash memory is one of the key components in those aspects. NAND flash provides higher density & faster operations moreover its array structure is bit complex, which demands an efficient controlling. In this paper we presented a generic NAND flash controller with the AXI host interface & Open NAND Flash Interface (ONFI). On the host side we use local interface which provides the flexibility to use different host protocols. While the ONFI is the standard interface which supports almost all vendors' NAND flash memory & adopts new NAND products. Presented design of controller can supports up to 32 Gb memory with one die & one channel. Design works on Single Data Rate (SDR) & supports basic memory operations. Error Correcting Code (ECC) is also added in design for data integrity. Moreover the design is configurable so that in future one can add more functionality. The design is verified with unit based verification.