Design of two dimensional reconfigurable cache memory using FPGA
Safaa S. Omran, Ibrahim A. Amory · 2016
In this paper VHDL (Very high level Hardware Description Language) is used to design and implement a Two Dimensional Reconfigurable Cache memory (cache size and associativity) using FPGA(Field-Programmable Gate Array). In this design the cache memory architecture allows to change the memory organization and size of its memory by using a cache size controller unit and way controller unit, to improve the processor performance and reduces the energy consumption, and using all available memory size for all possible organization that can be selected. The results show the simulation of the design. This design is synthesized using (Xilinx ISE Design Suite 13.4) and simulated using (Xilinx ISim simulator).