Fault-tolerant on-chip networking through adaptive routing and dynamic partial reconfiguration
Taimour Wehbe, Xiaofang Wang · Application-Specific Systems, Architectures, and Processors · 2014
Packet-switching on-chip networks are anticipated to become the communication infrastructure in the near future for multi-core processors and systems-on-chip. Increasing chip densities and high clock frequencies present major challenges to manufacturing reliable circuits. Fault tolerance in networks-on-chip is considered one of the vital characteristics of a system that requires fast and reliable communication between its nodes. In this paper, we explore fault-tolerant solutions through routing and partial reconfiguration under permanent link or router failures. No redundant resource is needed to support fault tolerance. We present a new XY routing algorithm and take advantage of partial reconfiguration to make sure all processing elements (PEs) stay connected to the network. The proposed routing algorithm is proven to be livelock and deadlock-free. Simulation results show that even if up to 20% of the links in the network are faulty, the new reconfigurable architecture and algorithm manage to route packets around such faults, and deliver them to their destination in a relatively low latency. In addition, results show that our complementary design makes the network tolerant to faults happening on various routers of the network, whether it is a center, border, or corner router. The design is synthesized and implemented on Xilinx Virtex-6 FPGAs. Synthesis reports show that our design provides the fault tolerant characteristic without incurring any area or speed degradation.