FPGA prototyping and parameterised based resource evaluation of Network on Chip architecture
Ayas Kanta Swain, Kunda Rajesh Babu, Sourav Narayan Satpathy, Kamala Kanta Mahapatra · 2016
This paper investigates the various aspects of network on Chip(NoC) design and its FPGA implementation. A parametric approach of evaluating the FPGA resources, delay and maximum frequency of operation for a NoC design has been described which may help the designer to take early decision related to NoC designing and prototyping. Virtual channel(VC), flit buffer depth and flit data width are taken as the parameter for evaluation. The functional simulation results show a successful data transfer between different nodes of a 3×3 NoC. Increase in VCs increases the FPGA resources, delay and reduces the frequency of operation. The maximum frequency of operation is also affected by the variation of Flit Data Width and Flit Buffer Depth.