Overhead-aware schedulablity analysis on responsive multithreaded processor
Yusuke Kumura, Keigo Mizotani, 雅義 高須, Hiroyuki Chishiro, Nobuyuki Yamasaki · Computers and Their Applications · 2015
In recent real-time systems, having multicore or simultaneous multithreaded (SMT) processor is now widespread. Considering the complexity of today’s architecture, predicting the behavior of task execution is challenging. And this has become a severe problem in real-time systems because estimating worst-case execution time (WCET) of tasks is important in constructing a dependable and accurate real-time systems. In this research, we provide overhead-aware schedulability analysis on a SMT processor. We take measurementbased approach in order to estimate WCET of tasks by measuring various runtime overheads that a realtime OS poses, because runtime overheads have a considerable impact on systems. Those measured overheads should be incorporated in schedulability analysis to evaluate the system more accurately. We target Dependable Responsive Multithreaded Processor (DRMTP), an 8-way SMT processor, to estimate runtime overheads, and conduct a series of schedulability analysis with measured runtime overheads considered. Our evaluation shows that the advantage of having context cache mechanism, the unique functionality of D-RMTP, can improve schedulability by up to 15.9%.