Hardware accelerator for data anonymization using dynamic partial reconfiguration
Sota Sawaguchi, Hiroaki Nishi · 2016
Smart City is a promising infrastructure for our near future community systems. It is predicted that more and more sensor devices and computing resources will be deployed in access networks because of the Internet of Things (IoT). This movement can create a wide variety of new applications with different requirements of delay, privacy and locality. Smart community dictates less than 10ms communication as a control interval in order not to disturb the lifeline systems, such as power supply. As such, future devices should have the following attributes: low-power, low-latency, and flexibility for various applications. In this paper, we propose an energy-aware, low-latency, and flexible local device, such as gateway or coordinator, which integrates an SoC FPGA with dynamic partial reconfiguration (DPR) feature to grapple with data anonymization. The data anonymization is important to protect private information in smart community because domestic human activities can be, for example, estimated by exploiting electric power consumption data, which is known as nonintrusive load monitoring (NILM). However, anonymization operations usually require processing cost at the order of O(n2) where n denotes the number of data in a privacy processing window. In case of encapsulating privacy information in a local network, privacy preserving computation should be achieved in a local device. Hence, we have implemented four primitive operations using DPR for various anonymization purposes. The proposed system achieves 18-328 times better performance and 10-200 times lower power consumption in every primitive anonymization method than Raspberry Pi 2 Model B.