A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure
T. Yamagata, M. Mihara, Takeshi Hamamoto, Toshifumi Kobayashi, M. Yamada · 2002
The authors describe a 288-kb (8 K words*36-b) fully parallel CAM (content addressable memory) LSI using a compact dynamic CAM cell (66 mu m/sup 2/) with stacked capacitor structure and a novel hierarchical priority encoder. The chip size is 10.3*12.0 mm/sup 2/, and the typical cycle time is 150 ns using circuit simulation. This CAM LSI performs large-scale search operations very efficiently, and therefore has the possibility of broad applications to high-performance artificial-intelligence machines and relational database systems.>