PERFORMANCE MACRO-MODELING TECHNIQUES FOR FAST ANALOG CIRCUIT SYNTHESIS
Glenn Wolfe · OhioLink ETD Center (Ohio Library and Information Network) · 2004
The synthesis of large digital integrated circuits is ubiquitous, highly developed, and efficient. Designs exceeding hundreds of millions of transistors are common and relatively inexpensive from a consumer view-point. Mature and reliable CAD tools exist for nearly every aspect of the digital design process. In contrast, the design of analog integrated circuits is often left to human designers utilizing first order approximation, experience, and iteration. Though the physical size of an analog block is typically orders of magnitude smaller than the digital part of a mixed signal IC, the analog design time often dominates. One of the main challenges in analog design is sizing. Given an analog topology and a set of high-level design constraints, the size of all components in the circuit must be appropriately determined while hope-fully meeting all design constraints. There are many ways to approach the sizing problem, from first-order approximation and manual design, to global optimization engines utilizing the full power of SPICE simula-tion. An analog topology is typically characterized by a set of performance parameters used to succinctly quantify the properties of the circuit. The behavior of the performance parameters is often coupled and highly nonlin-ear. The numerical circuit simulator SPICE is often used as a benchmark of comparison for evaluating the