A 16 Mbps adapter chip for the IBM token-ring local area network
K.W. Lang, C.K. Erdelyi, J.L. Lamphere, S.F. Oakland, J.D. Blair, Anthony Correale, H.C. Cranford, D.A. Dombrowski, C.R. Hoffman, J.K. Lee, J.M. Mullen, V.R. Norman · 1989
A 9.02-mm×9.02-mm chip built in 1-μm CMOS with two levels of metal and an addition mask level for fabricating capacitors is described. It contains both analog and digital circuits and has provisions for self-test. The functions include the transmitter, receiver, protocol handler, and microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. 24 K circuits of standard cell gates, 10 K circuits equivalent hand-honed custom microprocessor, and an analog macro form the physical design terrains. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s