Beyond 100Gbps Encoder Design for Staircase Codes
Guanghui Hu, Jin Sha, Zhongfeng Wang · 2016
The emergency of mass-data-processing applications encourages the exponential growth of high-speed communication technologies. In order to ensure the accuracy of data transmission, product codes have attracted much attention in both communications and storage industries. It is well-known that product codes are very efficient in achieving high coding gain and high throughput at low computation complexity. Unfortunately, VLSI architectures for either encoder or decoder of product codes close to 100Gbps data rate is rarely discussed in public literature. In this paper, a high-speed architecture for staircase codes, for the first time, is introduced and the corresponding encoder is implemented with a low-comlexity parallel BCH encoder. The implementation results at 90nm COMS technology show that the proposed encoder can operate at a frequency of 500MHz and with a guaranteed throughput of 119.5Gbps which fully meets the general requirements of optical transport network (OTN).