Floating-point datapaths with online built-in self speed test
Y. Hagihara, Shutaro Inui, Fuyuki Okamoto, M. Nishida, Takahiro I. Nakamura, H. Yamada · IEEE Journal of Solid-State Circuits · 1997
This paper describes floating-point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 291 MFLOPS vector pipelined processor for use in supercomputers. A new online test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which has traditionally been difficult.