Optimal hardware implementation of a low cost multiplier using multifunctional registers with decoded mode inputs
Mihai Grigore, Alexandru Valachi · 2016
In this paper, the authors propose a new optimal method for hardware implementation of a multiplication algorithm using multifunctional registers (MFR) with decoded inputs, based on transfer matrix method. The implementation cost is calculated emphasizing the most economical solutions. Low cost is taken into account. The modern design tools handle digital systems with many outputs and represent them by cubes, for efficiency reasons. Talking as optimal, hardware implementation of the digital automata can be reduced to a combinational one: synthesis using logic gates primitives and using floor planning design. The digital logic network that generates the control signals of the Finite State Machine (FSM can be synthesized using transfer matrix.