Using reconfigurable multi-core architectures for safety-critical embedded systems
Tom Guillaumet, Aayush Sharma, Éric Féron, Madhava Krishna, Ranjani Narayan, Philippe Baufreton, François Neumann, Emmanuel Grolleau · 2016
With the onset of multi- and many-core chips, the single-core market is closing down. Those chips constitute a new challenge for aerospace and safety-critical industries in general. Little is known about the certification of software running on these systems. There is therefore a strong need for developing software architectures based on multi-core architectures, yet compliant with safety-criticality constraints. This paper presents a reconfigurable multi-core architecture and the safety-criticality constraints for airborne systems. The last section uses the current certification guidance to explain how the architecture can satisfy these constraints even with dynamic features activated.