Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit
Masato Matsubayashi, Akashi Satoh, Jun Ishii · 2016
SAKURA-G (Side-channel AttacK User Reference Architecture - G) board equipped with two Spartan-6 FPGAs was developed for physical attack experiments against a cryptographic circuit as a successor to SASEBO-GII. In this work we developed a clock manipulator for SAKURA-G, which generate glitch noises to provoke malfunctions on a cryptographic circuit. By using the DCM (Digital Clock Manager) and PLL (Phase Locked Loop) of the Spartan-6 FPGA, precise control of the glitch injection was achieved. Through fault injection attack experiments against AES (Advanced Encryption Standard) circuit, the advantage of SAKURA-G over SASEBO-GII is demonstrated.