A general procedure for datapath and control design and its description in SystemVerilog
Botond Sándor Kirei, Marina Ţopa, Sorin Hintea · 2016
This paper presents a general procedure for datapath and control design, an example and a proposed laboratory work. The objective of the procedure is to transform a pseudo code (or a code written in a functional programming language) of an algorithm into a synthesizable HDL description. The procedure is general enough to be applied on simple algorithms (a few variables, value assignments and repetitive cycles). As an example, a simple C function is transposed to a SystemVerilog synthesizable code based on the proposed procedure. The laboratory work for student classes aims to exemplify HDL concepts, such as structural/behavioral, synthesizable/non-synthesizable HDL description and datapath/control design.