Timing verification of dynamic circuits
Kripasagar Venkat, Liang Chen, Ichiang Lin, Pravin Mistry, Pankaj M. Madhani · IEEE Journal of Solid-State Circuits · 1996
A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits.