A Comprehensive Evaluation of Direct and Indirect Network-On- Chip Topologies
Mehdi Baboli, Nasir Shaikh Husin, Muhammad Nadzir, Marsono Marsono · 2014
Over the last few years, there has been dramatic need for developing multi-processors with higher processing capability with area constraint. The interconnect topology for the processors make a significant contribution to area and network parameters such as average latency, power consumption, packet loss and buffer size. The current research is aimed at contributing to the field of Networks on-Chip (NoCs) design methodology. Many of the solutions proposed are simply borrowing the architectures and topologies from the interconnection networks for parallel architectures field and integrating them on-chip that can be used making load balance in a NoC. Although many aspects directly related to the on-chip context have been addressed, like load balance and power consumption or clock distribution and synchronization (asynchronous designs), it still appears that the proposed solutions are not fully centered around the “on-chip” context. The proposed research aims at developing a design methodology that fully uses the many other advantages of on-chip context. A construction by example is followed in building the methodology. This paper reviews some direct and indirect NoC topologies and their performance.