A reconfigurable near-data systolic array accelerator for the three-dimensional DRAM systems
Shu-Yen Lin, Jin-Yi Lin, Cheng-Hung Dixson Lin · 2016
In this work, we propose a reconfigurable near-data systolic array accelerator (NDSAA) for the 3D DRAM systems. The NDSAA supports the iterative operations for different applications, and the data movement between the processor core and the 3D DRAM is reduced. In our experiments, the 3D DRAM stacking the NDSAA reduces the latency by 51% ~ 70% compared to the one stacking the general bi-directional systolic array.