A scalable pipelined architecture for fast buffer SRAMs
Chris Nicol, Alex G. Dickinson · IEEE Journal of Solid-State Circuits · 1996
The design of synchronous buffer SRAMs for packet switching and signal processing applications is described. Called scalable cellular RAM (SCRAM), the approach configures memory blocks in a 2-D array with fully pipelined address and data distribution. The memory is scalable in that the access frequency is determined by the access time of a single block and is independent of the number of blocks. An experimental 0.5 /spl mu/m CMOS 256 Kb SCRAM chip is described that operates at 240 MHz. Simulation results show that larger arrays are feasible using the suggested power reduction and redundancy techniques.