Reduction of cache energy by switching between L1 high speed and low speed cache under application of DVFS
Kaoru Saito, Ryotaro Kobayashi, Hajime Shimada · 2016
Recent CPU widely utilizes cache memory or cache to decrease access speed gap between the CPU and the main memory. However, the cache occupies a large part of the processor's energy consumption. Furthermore, due to the characteristics of SRAMs, it is hard to reduce the supply voltage of the cache compared to that of the CPU core. Thus, dynamic voltage and frequency scaling (DVFS) which is widely used to reduce the processor's energy consumption does not reduce cache energy significantly. To confront this problem, we investigated a method which applies different power and speed design caches and switching them in proportion to the DVFS activity. Our proposal modifies the L1 cache hierarchy to L1 low-speed cache and L1 high-speed cache and selects them or access in sequential in proportion to DVFS activity to reduce cache energy demand. We confirmed that the proposal has a potential for further reduction of cache energy consumption with both cache design simulation and processor architecture level simulation.