VHDL Design and Implementation of C.P.U by Reversible Logic Gates
Devarasetty Vinod Kumar, Tata Jagannadha Swamy · International Journal of Advanced Scientific Technologies in Engineering and Management Sciences · 2016
Digital system implemented by using conventional gates like AND and OR gates dissipates a major amount of energy in the form of bits which gets erased during logical operations. This problem of energy loss can be solved by using reversible logic circuits in place of conventional circuits. Reversibility has become the most promising technology in digital circuits designing. In today's world C.P.U is one of the very important parts of any system having A.L.U applications for computers, cell phones, calculators etc. In this paper the design of 8-bit reversible C.P.U using reversible logic gates is proposed. The proposed C.P.U is analyzed on FPGA SPARTAN6 device. The proposed design is compared in terms of propagation delay, memory used and garbage outputs. In this paper the 8-bit reversible A.L.U and reversible logical unit is designed using Feyman, Peres, DKG and N.S gates. A memory block is designed with a row and coloumn addresses and organized to form a reversible C.P.U .