A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform
Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro · 2016
TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing many-core processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor. We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the two-dimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.