Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCs
Melika Tinati, Somayyeh Koohi, Shaahin Hessabi · 2016
Coping with the intrinsic limitations of electrical networks-on-chip, optical on-chip interconnect is emerged as a promising paradigm for future high performance multi-core designs. However, optical networks-on-chip (ONoCs) are drastically vulnerable to on-chip thermal fluctuation. Specifically, electrical power consumed by processing cores induces temperature drift, which may cause false paths for optical data communication through the network. Therefore, customizing electrical power distribution throughout the chip plays a critical role for reliable data communication in ONoCs. On the other hand, chip-scale distribution of electrical power is directly affected by mapping various applications with different power budget to on-chip cores. In this manner, although application mapping strategy is usually customized at the system-level, it potentially impacts physical-level failure rate of optical components in ONoCs. Emphasizing application-based fault behavior in optical networks, this paper explores network-level fault rates in ONoCs for application mapping and power distribution throughout the chip. For this purpose, we adopt a novel wavelength-routed Mesh-based optical NoC, and investigate its temperature-induced fault rate under various communication patterns and different mapping strategies of SPEC 2000 benchmark applications. Simulation results indicate that although mapping strategy does not considerably affect network fault rate. Employing various communication patterns can effectively lead to fault rate variation in a Mesh-based ONoC. Specifically, for every 30% increase in traffic locality percentage, network fault rate decreases by 20%.