Experimental Calibration and Validation of a Speed Scaling Simulator
Arsham Bryan Skrenes, Carey L. Williamson · 2016
In this paper, we use experimental measurements to calibrate and validate a discrete-event simulator for dynamic speed scaling systems. The experimental implementation work is carried out in an Ubuntu Linux environment using a quad-core 2.3 GHz Intel i7 processor with the Ivy Bridge micro-architecture. Our implementation provides fine-grain user-level control of process execution, and uses the Running-Average Power Limit (RAPL) Machine Specific Registers (MSRs) to track energy usage. Through careful micro-benchmarking experiments, we determine the power consumption for each of the 12 discrete speeds supported by the processor, while also quantifying the costs of context switches and CPU speed changes. Finally, we use our suitably-parameterized speed scaling simulator to evaluate three different CPU speed scaling algorithms from the literature on simple batch workloads. To the best of our knowledge, our paper provides the first direct comparison of these speed scaling strategies with realistic system costs.