Efficient Floating Point Multiplier Implementation via Carry Save Multiplier
Padala Siva Kumar, Chirag Patel, S. Sivanantham · 2014
The demand for floating point multiplication is increasing day by day since it supports wide range of multimedia applications. So floating point multiplication becomes essential in the domain of image processing, data extraction and digital signal processing. In this proposed paper, a single precision floating point multiplier is designed. The design of integrated chip in term of power, area and speed has a challenging problem now a days. The demand for low power VLSI circuits is increasing day by day. So, the main contribution of this paper is to reduce the power consumption. This has been achieved by designing a carry save multiplier. Here by reducing the number of adders required for partial product addition Carry look ahead adder is used for the addition of exponents in order to reduce the overall timing delay of design.