VLSI efficient search estimation video compression algorithm
P Rajendra Prasad, K N Sunil Kumar, Shivashankar, Arjun Kumar GB · 2016
In video compression, one needs a highly efficient motion estimation algorithm in terms of processing speed. A novel block matching algorithm for motion estimation in a video frame sequence well suited for a high performance VLSI implementation is presented in this project. The algorithm is up to 40% faster when compared to one of the fastest existing algorithms, viz., one-at-a-time step search algorithm without compromising either in the image quality or in the compression affected. The speed advantage is preserved even in the event of a sudden scene change in a video sequence. The proposed fast one step search algorithm is also capable of dynamically detecting the direction of motion of image blocks. The FPGA implementation of the algorithm is capable of processing color pictures of sizes up to 1024×768 pixels at the real time video rate of 30 frames per second and conforms to H.264 standards. This paper proposes the implementation of a VLSI Efficient Search Estimation Video Compression Algorithm, where the quality of image is maintained without sacrificing the image quality using Verilog and Mat lab.