Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays
Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich · 2016
On processor arrays, combining modulo scheduling with tiling would increase the degree of parallelism compared to both in isolation. However, tiling must be symbolic to yield input-size independent code, making the tile size unknown at compile time and introducing parameters into the dependence constraints. Existing solutions to symbolic tiling have, however, so far ignored modulo scheduling. In this paper, we present a compiler algorithm that integrates modulo scheduling with symbolic tiling: the dependence constraints are partitioned into a parametric- and non-parametric subset and, using only the non-parametric constraints, we find a solution to the modulo scheduling problem. To still satisfy the parametric dependence constraints, we calculate a minimum tile size from the found solution. If the minimum tile size is not satisfied at runtime, a fallback schedule is instead chosen. We formally and experimentally show that, if the number of processor elements to map to is known at compile time, the resulting schedules are latency-optimal; otherwise, they are negligibly nonoptimal.