Design and analysis of adder architectures in Multiple constant Multiplication (MCM) in fixed width reconfigurable FIR architecture
S. Muralirajan, S. Sivasundarapandian · 2016
In this paper a work can be proposed in order to deliver that the Multiple constant Multiplication method is effective when we design an FIR Filter with direct form architecture with the possibility that it can become programmable transpose form Architecture and it configures into block FIR filter for the area and delay comprehension of many order FIR filters for both fixed and Rearranged the Blocks Designed by using HDL Language and then Simulated using Model-Sim 6.3c synthesized using Xilinx ISE 12.1. Between these two architectures and we find out the Area, Delay and Power and their values for the corresponding Field Programmable Gate Array (FPGA) are Determined.