Design of 16∗16 high speed MLM using KOM for image filter applicaton
Ashwini Mekkalaki, Meghana S. Kulkarni · 2016
Now a day's digital signal processing applications such as biometric trait images, satellite imaging, medical imaging, mainly depends on the multipliers to improve quality of image. But existing Logarithmic multiplier techniques produces error in the output and also they require more time for calculation. Hence it is necessary to nullify the error and increase the speed of operation. To nullify the error and increase the speed delay. of the operation of the Logarithmic Multiplier, 16×16 “Mitchell Log Multiplier” (MLM) using “Karastuba Ofman Multiplier” is implemented. In this project Mitchell Log Multiplier with zero error is implemented for image filters. The higher order 16×16, 8×8 Multipliers are designed using KOM. The higher order KOM multipliers are divided into number of lower order multipliers using till basic block of order 4×4 is obtained using radix 2. 4×4 Mitchell Log Multiplier is designed with zero error by introducing error correction circuit. Further the 8×8 “Mitchell Log Multiplier” is tested for Gaussian filter to remove noise in image. The project model is simulated using Xilinx 14.5 and synthesized using Spartan 6 FPGA family kit. The performance parameters such as speed, error area utilization and PSNR are evaluated. It is observed that using Mitchell log multiplier zero error is obtained for multiplication operation and PSNR of 25.11 DB and delay of 6.629ns is obtained.