Feasibility of mapping a pulsed RADAR system to FPGA-ASIC and hybrid architectures
Mohammed A. S. Aseeri · 2016
Current trends in front end radar processing have dynamically evolved with the rapid development and integration of Field Programmable Gate Array (FPGA) technologies meriting high speed digital data processing (DSP) capabilities. The meritocracy of FPGAs depends on Fast real time Impulse Response (FIR) filtering algorithms and applications added in the rapid adoption and integration of FPGAs for Radio Detection and Ranging (RADAR) signal processing. The state of FPGA technologies underpin the migration from Large Scale Integration (VLSI) chips in radar signal processing to the reconfigurable technologies. Various FPGA devices and underlying technologies were investigated in this paper with a specialized bias on the ability to implement them on the underlying hardware with a broad base for flexibility and reconfiguration. The results show that parallel signal processing provides better signal processing compared with serial processing because of the flexibility in linear-systolic design placements, use of shift registers and real time memory retrieval capabilities, and use of two banks of coefficients to avoid using constant coefficients. However, there is need for further research on how to design chips with higher processing powers that can accommodate new versions of hardware and software.