Static energy reduction by performance linked dynamic cache resizing
Shounak Chakraborty, Hemangee K. Kapoor · 2016
The increased power density with short channel effect in modern transistors significantly increases the leakage energy consumptions of on-chip Last Level Caches (LLCs) in recent Chip Multi-Processors(CMPs). Performance linked dynamic shrinking in the LLC size is a promising option for reducing cache leakage. Prior works attempt to reduce the cache leakage by predicting Working Set Size(WSS) of the applications and by putting some cache portions in low power mode. This paper aims to reduce leakage energy by using a combination of cache bank shutdown and way shutdown. The banks with minimal usages are candidates for shutdown. In banks with average usages, some ways are turned off to save leakage. To mitigate the impact of smaller set-size, we apply dynamic associativity management technique. Experimental evaluation using full system simulation on a 4MB 8-way set associative L2 cache gives 70% average savings in static energy with 35% average savings in EDP. In case application's cache demand increases we can turn-on some ways to maintain performance.