Design and Implementation of Smart Reliable Router Switch for Dynamic NOC
Kakarla Amaravathi, Abhay K. Meshram · 2014
In this paper we presented new router architecture, it includes an advance routing logic and error detection mechanism. So it is well suitable for the network under heavy traffic conditions .This proposed algorithm gives a better solution to avoid livelock and deadlock conditions. it will shows 100% of the error detection .In this proposed algorithm the Network on Chip (NoC) data packets are protected by using error correcting code(ECC) of hamming and switch-to-switch error detection. The designed NoC architectures are simulated and the required parameters are calculated using the tool ModelSim, which is used as a simulation and debugging tool for VHDL, verilog and mixed language designs and the tool Quartus, which is used to synthesis the network designed using VHDL Hardware description language.