CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era
Venkata Yaswanth Raparti, Nishit Kapadia, Sudeep Pasricha · 2016
Transient faults due to single and multiple bit-flips are becoming increasingly common in today's multicore processing chips and reduce overall chip reliability. Simultaneously, aging effects due to phenomena such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) also gradually reduce chip reliability over time. Unfortunately, with technology scaling, the increasingly stringent on-chip dark-silicon power constraints prohibit costly fault resilience solutions. Clearly, a viable approach is needed that can address both transient- and aging-induced faults in emerging multicore chips, but this is not easy. For example, techniques to slow down aging typically increase susceptibility to transient faults and vice-versa. In this paper, we propose a novel runtime framework (CHARM) to manage the useful chip lifetime, while also addressing transient faults and meeting performance and dark-silicon constraints. Experimental results on a 60-core chip multiprocessor show that CHARM not only achieves transient fault resilience while satisfying dark-silicon constraints, but also achieves an improvement of up to 2.5× in lifetime, and up to 6× in number of applications executed over the chip lifetime compared to a state-of-the-art solution.