Design and Integration of New Architecture Features into a Many-Core Chip Architecture - A Report on a Novel Architecture/Software Co-Verification Platform
Juergen Ributzka, Yuhei Hayashi, Guang R. Gao · 2010
Historically, design and integration of a new architectural feature requires time consum-ing full system verification/validation. This challenge is particularly serious for the research and development of multi-/many-core chips due to the scale of the chip and time-to-market constraints. We conducted a logic design and integration of a new architecture feature, called Synchronization State Buffer (SSB) into the IBM Cyclops-64 (C64) many-core ar-chitecture logic. We used DEEP, a FPGA-based emulation platform that was developed for the purpose of hardware/software co-verification of the C64 chip. Our experiences have demonstrated the following key features are critical to achieve our objectives: Fast compilation of the logic design is very important during the early stages of the logic design to allow for quick turn-around times. To this end, the full C64 chip logic can be compiled under two minutes for software simulation. Full-System hardware emulation with debugging support is crucial for whole chip logic verification- some deep, concurrency-related bugs may be exposed only after many cycles of full chip parallel execution. DEEP’s emulation mode allows such bugs to be found very fast- in minutes, which would have taken otherwise years with software simulation. High-Speed hardware emulation (over 20KHz) of the whole system allows us to run entire parallel applications. This allows the experimentation of novel program and code generation paradigms within reasonable time. Our experience show that future many-core research and development could greatly benefit from advanced emulation paradigms as we have explored in this study. 1