Evaluation of Cache Memory Parameters with Different Instruction Set Architectures
N. Ramasubramanian, Hathiram Banoth · 2013
Latest advancements in multi-core have created interest among many research groups in exploring and finding out ways to harness the true power of large number of processor cores. Therefore, multi-core systems have become the dominant architecture for desktop, high-performance and handheld devices. Several chip manufacturers including AMD, IBM, Intel and Sun have released systems, which have multiple processing units on a single chip. This trend is likely to continue with more and more cores being put on a single chip. However, these architectures have introduced many challenges in maximizing the application performance. Thus, performance evaluation of the multi-core architectures becomes very important to unveil the potential of these systems. In order to analyse the experimental results better, an architectural overview of the experimental test-bed is provided. In addition, experimental methodology and the targeted performance metrics are described. Cache memory read latency is measured for varying memory sizes up to 8MB for 64bit stride memory accesses. The entire memory hierarchy is measured starting from the L1 cache to the main memory. Results of M5sim conducted on AMD Opteron 2218 shows a reduced access time compared to the results obtained from ALPHA ISA, AMD Opteron 2218 shows the better performance than ALPHA 21264(EV 6).