Quasi-Shared Output Buffer Switch
Dan Keun Sung, Sy Nam, KS Sohn · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2001
Summary One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the separated buffers by using a distributor for each output port. These separated buffers can lower the memory speed. Since each input has its own cell path independent of other inputs, cell contentions do not occur at the input ports and no speed-up is needed. The performance of the proposed switch is evaluated in terms of the average cell latency compared with the conventional input buffered switches which use the iSLIP and wrapped wave front arbitration (WWFA) algorithms.