Studying an SoC with Virtual Self-timed Blocks using MATLAB Simulink
Yuan Chen, Fei Xia, Delong Shang, Alex Yakovlev · 2008
In order to increase the power efficiency of IP cores in an SoC, a Self-timed Event Processor (STEP) is modelled and designed in our previous research to provide power management and event handling for each IP core in a frame of Virtual Self-timed Block (VSB). This paper presents the construction of an example SoC with four VSBs in MATLAB Simulink where a test bench named as “ball game” was implemented. The benchmark achieved from MATLAB Simulation verified the correctness and efficiency of our STEP design.