MINIMIZING TEST POWER IN VLSI ARCHITECTURE USING BIST BASED LOW-TRANSITION TEST PATTERN GENERATION TECHNIQUE
J Praveen · 2014
The Integrated circuit (IC) contains Built-In Self-Test (BIST) and circuit under test (CUT), to test the correct functionality of any integrated circuit, test patterns are generated from Built In Self Test and then same generated test patterns are applied to the Circuit-under-Test (CUT), minimizing hardware overhead is a major concern of BIST implementation. In pseudo-random BIST design, the test vectors are generated with the help of Linear Feedback Shift Registers (LFSR) and which is called as conventional LFSR. The main drawback of these conventional LFSRs is, it generates normally more number of random natured test vectors for testing the CUT in which many are repeated patterns and application of which unnecessarily increase the test power without contributing much to the fault coverage. Apart from this, as the bulkiness of the CUT increases, the test vector generating engine is even becomes large in terms of number of sequential or test vector generating element. So that it could generate as many numbers of vectors which can fits the number of I/O pins of CUT logic or part of CUT logic. Thus, the increase in size of test circuit also requires the considerable die size on IC. This paper presents a new approach, called Linear feedback shift register -Bit complement test pattern generation technique (LFSR-BCTPG). In LFSR-BCTPG technique, the output bits are complemented due to which unrepeated test vectors are increased also by which better fault coverage with reduction in the bulkiness of the test circuit can be achieved. Hence, in this approach, the proposed test circuit can be half in size, compared to other conventional test circuits to test a particular CUT. The final results of proposed approach have been compared with other methods and found that, this method is better in terms of dynamic power dissipation when applying the test vectors generated by the proposed method to four different ISCAS'89 benchmark circuits.