Tolerating more hard errors in MLC PCMs using compression
Majid Jalili, Hamid Sarbazi‐Azad · 2016
Modern computer systems require fast, large and reliable memories to handle information explosion. With this goal in mind, not only deployment of main memories with new technologies are necessary, but also adopting innovative solutions for addressing newfound challenges must be considered as a priority. Recently, phase change memory (PCM) appeared as a preferred candidate for substituting DRAM. PCM with non-volatility, low static power consumption and storing multiple level cells (MLC) capability has opened a new way to the future of memories. Although PCM presents considerable potentials, its short lifetime is a critical concern. Worse still, adopting multiple bits per cell capability degrades the lifetime of PCM more quickly. Hence, convincing the industry for massive production of PCM needs effective and pragmatic solutions. In this paper, we extend the lifetime of a MLC PCM main memory by relying on two strategies: postponing the occurrence of stuck-at failures, and effectively tolerating hard errors. Our scheme postpones the occurrence of hard errors by converting blocks from MLC to SLC mode using byte-level compression. Employing some pointers, the proposed method attempts to cover hard errors by fitting a compressed block either in its physical line location or elsewhere in the page. Full-system and statistical evaluation of the proposed solution shows 48% lifetime improvement of the memory system along with 9% IPC improvement, compared to a state-of-the-art design.