Survey of ASIC implementations of LDPC decoders
Robert G. Maunder · ePrints Soton (University of Southampton) · 2016
This survey characterises the flexibility, throughput, area efficiency and energy efficiency of 62 different ASIC implementations of LDPC decoders. In general, the results show that increasing the number of supported parity check matrices by 10 times reduces each of the achievable throughput, area efficiency and energy efficiency by 10 times.