Memory design considerations for high-performance networking SoCs
Igor Arsovski, Qing Li, Mark Kuemerle, Rui Tu, Harold Pilo · 2013
On chip memory in today's networking SoCs takes up >50% of total area and consumes >40% of total power. As demand for high-performance networks grows, so will the memory content on future SoCs. This paper presents IBM's 32nm HKMG SOI embedded memory offering discussing the considerations associated with the design of key networking memory functions. With memory limiting system performance and dictating minimum voltage system-level power and performance optimization are also presented.