FPGA and ASIC
Amin Malekpour, Sadegh Nejatzadeh, Farzaneh Aghajari, Saeid Malekpour · 2015
Decimal multiplication is believed as a frequent operation with inherent complexity in implementation which is becoming more and more important every day. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system cannot ensure preciseness. In this paper a new architecture for parallel decimal multiplication is presented. Evaluation results for 16-digit operands show that the proposed architecture has 8.7% less energy/power consumption and improves area on ASIC and has 8.1% less energy consumption and improves power, delay and area on FPGA.