A GaAs FET chip-set and applications to secure communication
M. Conforti, J. Bertrand, J. Irvine, Hausila Prasad Singh, R.A. Sadler · 2002
In order to perform the real-time fast Fourier transmission required by secure communication systems at rates that can be as high as 20-30 MHz, the implementation of the FFT kernel, the butterfly, by a GaAs chip-set was undertaken. The basic parameters are set to a real-time bandwidth of 20 MHz and a spurious free dynamic range (SFDR) of 70 dB. The analysis partitions the FFT kernel into two chip types: one that performs complex multiplication, and a second, the spider, that performs the required additions and subtractions. Analysis indicates that a 16-bit*12-bit complex multiplier implemented in GaAs can perform a multiplication in less than 10 ns, and thus meets the real-time bandwidth requirements. A radix-4 implementation is often favored because of its higher efficiency and reasonable butterfly complexity. With a 10-ns butterfly, it is simple to show that a 16 K-point FFT, assuming memory matched to the arithmetic unit, can support a real-time sampling rate of approximately 57 MHz. A radix-2 implementation that supports a 14-MHz real-time sampling frequency and exhibits a less stringent 1.25-ns memory access requirement is also investigated.>