AN AREA EFFICIENT MCM BASED DIGITAL FIR FILTER FOR SIGNAL PROCESSING SYSTEM
S. Sai Sreelekha, C. Vijaya Bhaskar · 2015
This paper proposes the computationally efficient, low power, high speed partial reconfigurable 9-tap FIR filter design using multiple constant multiplication technique. To reduce reconfiguration time dynamic partial reconfiguration is introduced. Module-based dynamic partial reconfiguration is proposed for the realization of both low pass filter and high pass filters. Here the filters are dynamically reconfigured by modifying the coefficients of the filter. The 9-tap fir filter is to design in XILINX ISE. The design is implemented using ALTERA FPGA kit. This dynamic partially reconfigurable FIR filter design shows improvement in reconfiguration time, flexibility and area utilization.